(1) Field of the Invention
The present invention relates to a semiconductor integrated circuit device, in particular, relating to an effective technology for semiconductor devices which includes unit semiconductor storage devices in an arbitrary number.
(2) Description of the Prior Art
Conventionally, semiconductor storage devices are produced by forming a number of semiconductor storage devices having an identical capacity on a common wafer. This wafer is cut along dicing lines into pieces, i.e., individual semiconductor storage devices which in turn are packaged into products all having the same capacity.
Most semiconductor storage devices incorporate redundant circuits to some degree, assuming development of deficiency and faults during their manufacturing. Therefore, if a fault etc. develops, the defective portion will be replaced with its backup redundant circuit so that the semiconductor storage device will function normally.
The conventional semiconductor devices, however, suffered from the following problems. For example, in the production of 16 Mbit DRAMs as one type of the semiconductor devices, semiconductor storage devices of single type having an identical capacity (16 Mbits) are provided on a common wafer. Suppose that this 16 Mbit DRAM chip has a 5% redundant circuit ratio therein. In this case, if defects in the circuit or faults during production arise in an amount of 6% of the entire circuit, the chip is assumed as defective even when 94%, the remaining portion of the circuit functions normally, thus degrading production yield and increasing the cost of the chip.
In the case where 8 Mbit DRAMs, 4 Mbit DRAMs etc. are produced from 16 Mbit DRAMs using a designing technique called `cut-down process` disclosed in Japanese Patent Application Laid-Open Hei 4 No.373,169, needed storage circuits, controller circuits etc. must be diced out from 16 Mbit DRAMs, and then 8 Mbit DRAMs and 4 Mbit DRAMs need to be newly designed and produced. Therefore, this method needed time for designing and production.